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AVIEON has patented architectural enhancements in DSP
processor design using 4X fewer gates and memory for equivalent functionality,
resulting in significant cost reduction.
The SIDO (same instruction different operation) architecture allows for
much shorter / smaller instruction memory and far fewer register ports.
This provides a 4X performance improvement compared to conventional DSPs
and results in greatly reduced power consumption. The Neuron MSP is based
on standard cells and only dual port memory elements with no special cells
required to meet specifications. The AVIEON team has extensive experience
in processor and IP design, EDA design and verification tools, and fabless
IC manufacturing supporting tier-1 customers.
