Architecture

  • C programmable, multi-core, Video & Image Signal Processor (VISP)
  • SIDO (Same Instruction Different Operation)
  • SIMD architecture
  • High performance programmable data path (PDP)
  • Sophisticated Video 2D-DMA to offload the ARM CPU. Works in parallel with the ARM and MSP
  • Host CPU: 32-bit RISC ARM926EJ-S Core with 16 I/D cache minimum frequency 400MHz
  • System Bus: 64-bit AMBA 2.0 or PLB

VISP peak performance

  • 44.68 GOPS @ 266MHz – 42 operations / cycle.
  • 31.9 Million 16x16 SAD per second
  • Programmable single/multiple frame super resolution.
  • Supports up to 1920 x 1280 pixels
  • Enables real-time processing without an image distortion

Image processing algorithms

  • Smart image engine: High-Definition (HD) video super resolution with skin-tone and out-of-focus correction de-blur, image stabilization
  • Still picture up to 30 mega pixel.

Power consumption

  • Extremely low-power Video & Image Signal processor 0.11mW @ 1Mhz per VISP in 90nm CMOS

Deliverables

Hardware IP

  • Synthesizable encrypted Verilog code.
  • Corresponding DC synthesis scripts and synthesis constraint files
  • Integration guides and scripts
  • A reference (synthesized) design targeting to a reference library (CIC provided), and the corresponding area, timing, power, testability reports
  • Verilog and C verification environment and testbench (test patterns) files

Software IP

  • Customized executable running Avieon proprietary Super Resolution algorithms using VISP on Linux or Window
  • Executables running VISP regressions on a particular FPGA board
  • Test streams

Documentation

  • Functional description and architecture
  • Key features and claims
  • Configuration information and parameters
  • Comprehensive technical specification and data sheet
  • Test plan/methods and testability measurement
  • System-level verification and testing strategy
  • Application notes that instantiates the core.